1 ? fn9217.3 isl9000 dual ldo with low noise, very high psrr, and low i q isl9000 is a high performance dual ldo capable of sourcing 300ma current from each output. it has a low standby current and very high psrr and is stable with output capacitance of 1 f to 10 f with esr of up to 200m . the device integrates an individual power-on-reset (por) function for each output. the por delay for vo2 can be externally programmed by connecting a timing capacitor to the cpor pin. the por delay for vo1 is internally fixed at approximately 2ms. a reference bypass pin is also provided for connecting a noise filtering capacitor for low noise and high-psrr applications. the quiescent current is typically only 42 a with both ldo?s enabled and active. separate enable pins control each individual ldo output. when both enable pins are low, the device is in shutdown, typically drawing less than 0.1 a. several combinations of voltage outputs are standard. others are available on request. output voltage options for each ldo range from 1.2v to 3.6v. pinout isl9000 10 ld 3x3 dfn top view features ? integrates two 300ma hi gh performance ldo?s ? excellent transient response to large current steps ? 1.8% accuracy over all operating conditions ? excellent load regulation: < 0.1% voltage change across full range of load current ? low output noise: typically 30 vrms @ 100 a (1.5v) ? very high psrr: 90db @ 1khz ? extremely low quiescent current: 42 a (both ldos active) ? wide input voltage capability: 2.3v to 6.5v ? low dropout voltage: typically 200mv @ 300ma ? stable with 1 f-10 f ceramic capacitors ? separate enable and por pins for each ldo ? soft-start and staged turn-on to limit input current surge during enable ? current limit and overheat protection ? tiny 10 ld 3x3mm dfn package ? -40c to +85c operating temperature range ? pb-free plus anneal available (rohs compliant) applications ? pdas, cell phones and smart phones ? portable instruments, mp3 players ? handheld devices including medical handhelds vin en1 en2 cbyp cpor vo1 vo2 por2 por1 gnd 2 3 4 1 5 9 8 7 10 6 data sheet august 2, 2006 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2005, 2006. all rights reserved. all other trademarks mentioned are the property of their respective owners.
2 fn9217.3 august 2, 2006 ordering information part number (notes 1, 2, 3) part marking vo1 voltage (v) vo2 voltage (v) temp range (c) package (pb-free) pkg dwg. # isl9000irnnz dcga 3.3 3.3 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irnjz daaa 3.3 2.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irnfz dbaa 3.3 2.5 -40 to +85 10 ld 3x3 dfn l10.3x3c ISL9000IRNCZ dabh 3.3 1.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irmnz dcha 3.0 3.3 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irmmz dsaa 3.0 3.0 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irmgz dcja 3.0 2.7 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irllz draa 2.9 2.9 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irknz dabf 2.85 3.3 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irkkz dcaa 2.85 2.85 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irkjz ddaa 2.85 2.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irkfz deaa 2.85 2.5 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irkpz dabg 2.85 1.85 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irkcz dhaa 2.85 1.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irjnz dcka 2.8 3.3 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irjmz dpaa 2.8 3.0 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irjrz dnaa 2.8 2.6 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irjcz dmaa 2.8 1.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irjbz dfaa 2.8 1.5 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irgpz dabe 2.7 1.85 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irgcz dlaa 2.7 1.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irfjz dgaa 2.5 2.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irfdz dcla 2.5 2.0 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irfcz dcma 2.5 1.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irplz dkaa 1.85 2.9 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irppz dabj 1.85 1.85 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000ircjz dcna 1.8 2.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irccz dcpa 1.8 1.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irblz dabd 1.5 2.9 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irbjz djaa 1.5 2.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irbcz dabc 1.5 1.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9000irbbz dabb 1.5 1.5 -40 to +85 10 ld 3x3 dfn l10.3x3c notes: 1. add -t to part number for tape and reel. 2. for other output voltages, contact intersil marketing. 3. intersil pb-free plus anneal products empl oy special pb-free material sets; molding compounds/die attach materials and 100% m atte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow tem peratures that meet or exceed the pb-free requirements of ipc/jedec j std-020. isl9000
3 fn9217.3 august 2, 2006 absolute maximum rati ngs thermal information supply voltage (vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (v in +0.3)v recommended operating conditions ambient temperature range (t a ) . . . . . . . . . . . . . . .-40c to +85c supply voltage (vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 to 6.5v thermal resistance (notes 1, 2) ja (c/w) jc (c/w) 3x3 dfn package . . . . . . . . . . . . . . . . 50 10 junction temperature range . . . . . . . . . . . . . . . . .-40c to +125c operating temperature range . . . . . . . . . . . . . . . . .-40c to +85c storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . +300c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. jc , ?case temperature? location is at the center of the exposed metal pad on the package underside. see tech brief tb379. electrical specifications unless otherwise noted, all parameters are guarant eed over the operational supply voltage and temperature range of the device as follows: t a = -40c to +85c; v in = (v o +0.5v) to 6.5v with a minimum v in of 2.3v; c in = 1f; c o = 1f; c byp = 0.01f; c por = 0.01f parameter symbol test conditions min typ max units dc characteristics supply voltage v in 2.3 6.5 v ground current quiescent condition: i o1 = 0 a; i o2 = 0 a i dd1 one ldo active 25 32 a i dd2 both ldo active 42 52 a shutdown current i dds @25c 0.1 1.0 a uvlo threshold v uv+ 1.9 2.1 2.3 v v uv- 1.6 1.8 2.0 v regulation voltage accuracy initial accuracy at v in = v o +0.5v, i o = 10ma, t j = 25c -0.7 +0.7 % v in = v o +0.5v to 5.5v, i o = 10 a to 300ma, t j = 25c -0.8 +0.8 % v in = v o +0.5v to 5.5v, i o = 10 a to 300ma, t j = -40c to 125c -1.8 +1.8 % maximum output current i max continuous 300 ma internal current limit i lim 350 475 600 ma dropout voltage (note 4) v do1 i o = 300ma; v o < 2.5v 300 500 mv v do2 i o = 300ma; 2.5v v o 2.8v 250 400 mv v do3 i o = 300ma; v o > 2.8v 200 325 mv thermal shutdown temperature t sd+ 145 c t sd- 110 c ac characteristics ripple rejection (note 3) i o = 10ma, v in = 2.8v(min), v o = 1.8v, c byp = 0.1f @ 1khz 90 db @ 10khz 70 db @ 100khz 50 db output noise voltage (note 3) i o = 100a, v o = 1.5v, t a = 25c, c byp = 0.1f bw = 10hz to 100khz 30 vrms device start-up characteristics device enable time t en time from assertion of the enx pin to when the output voltage reaches 95% of the vo(nom) 250 500 s isl9000
4 fn9217.3 august 2, 2006 ldo soft-start ramp rate t ssr slope of linear portion of ldo output voltage ramp during start-up 30 60 s/v en1, en2 pin characteristics input low voltage v il -0.3 0.5 v input high voltage v ih 1.4 v in +0.3 v input leakage current i il , i ih 0.1 a pin capacitance c pin informative 5 pf por1 , por2 pin characteristics por1 , por2 thresholds v por+ as a percentage of nominal output voltage 91 94 97 % v por- 87 90 93 % por1 delay t p1lh 1.0 2.0 3.0 ms t p1hl 25 s por2 delay t p2lh c por = 0.01 f 100 200 300 ms t p2hl 25 s por1 , por2 pin output low voltage v ol @i ol = 1.0ma 0.2 v por1 , por2 pin internal pull-up resistance r por 78 100 180 k notes: 3. guaranteed by design and characterization. 4. vox = 0.98 * vox(nom); valid for vox greater than 1.85v. electrical specifications unless otherwise noted, all parameters are guarant eed over the operational supply voltage and temperature range of the device as follows: t a = -40c to +85c; v in = (v o +0.5v) to 6.5v with a minimum v in of 2.3v; c in = 1f; c o = 1f; c byp = 0.01f; c por = 0.01f (continued) parameter symbol test conditions min typ max units v por+ v por+ v por- 5 fn9217.3 august 2, 2006 typical performance curves figure 2. output voltage vs input voltage (3.3v output) figure 3. output voltage change vs load current figure 4. output voltage change vs temperature fi gure 5. output voltage vs input voltage (3.3v output) figure 6. output voltage vs input voltage (2.8v output) figure 7. dropout voltage vs load current output voltage, vo (%) input voltage (v) -0.6 -0.2 0.2 0.6 -0.8 3.8 4.2 6.2 5.8 6.6 3.4 4.6 5.0 5.4 -0.4 0.0 0.4 0.8 vo = 3.3v 85c -40c 25c i load = 0ma 0.04 0.06 -0.06 -0.10 100 200 300 400 0 load current - i o (ma) output voltage change (%) -0.02 0.00 0.02 0.08 0.10 -0.04 -0.08 50 150 250 350 vin = 3.8v vo = 3.3v 85c -40c 25c 0.04 0.06 -0.06 -0.10 -10 20 50 110 -40 temperature (c) output voltage change (%) -0.02 0.00 0.02 0.08 0.10 -0.04 -0.08 -25 5 35 80 65 95 125 vin = 3.8v vo = 3.3v i load = 0ma output voltage, vo (v) input voltage (v) 3.0 3.1 3.2 3.3 3.4 2.9 2.8 3.1 3.6 4.1 4.6 5.1 6.1 5.6 i o = 300ma i o = 150ma i o = 0ma vo = 3.3v 6.5 2.5 2.6 2.7 2.8 2.9 2.4 2.3 2.63.13.64.14.65.1 6.1 input voltage (v) output voltage, vo (v) 5.6 i o = 0ma i o = 300ma vo = 2.8v i o = 150ma 6.5 200 250 300 350 150 100 50 0 50 100 150 200 250 300 350 400 0 output load (ma) dropout voltage, v do (mv) vo = 2.8v vo = 3.3v isl9000
6 fn9217.3 august 2, 2006 figure 8. dropout voltage vs load current figure 9. ground current vs input voltage figure 10. ground current vs load fig ure 11. ground current vs temperature figure 12. power-up/power-d own figure 13. power-up/power -down with por signals typical performance curves (continued) 200 250 300 350 150 100 50 0 50 100 150 200 250 300 350 400 0 output load (ma) dropout voltage, v do (mv) vo = 3.3v 85c 25c -40c 30 35 40 45 55 25 4.0 5.0 6.5 input voltage (v) ground current (a) 50 3.0 3.5 4.58 5.5 6.0 i o (both channels) = 0a vo1 = 3.3v vo2 = 2.8v -40c 25c 125c 200 160 100 20 0 50 100 150 200 250 400 0 load current (ma) ground current (a) 350 300 vo1 = 3.3v vin = 3.8v vo2 = 2.8v 40 60 80 120 140 180 85c -40c 25c 35 25 -10 20 50 110 -40 temperature (c) ground current (a) 45 50 55 40 30 -25 5 35 80 65 95 125 vin = 3.8v vo = 3.3v i load = 0a both outputs on 2 3 4 5 1 0 1234567 10 time (s) voltage (v) 89 vo2 vo1 vin 0 vo1 = 3.3v vo2 = 2.8v i l 1 = 300ma i l 2 = 300ma 1.5 2.0 2.5 3.0 1.0 0.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 5.0 0 time (s) voltage (v) 4.0 4.5 por1 vo1 por2 vo2 0 3.5 vo1 = 3.3v vo2 = 2.8v i l 1 = 300ma i l 2 = 300ma cpor = 0.1f isl9000
7 fn9217.3 august 2, 2006 figure 14. turn on/turn off response figure 15. line transient response (3.3v output) figure 16. line transient response (2.8v output) figure 17. load transient response figure 18. psrr vs frequency figure 19. spectral noise density vs frequency typical performance curves (continued) 1 3 0 2 0 100 200 300 400 500 600 700 800 0 time (s) vo1 (v) ven (v) 5 vo1 = 3.3v vin = 5.0v i l 1 = 300ma c l 1, c l 2 = 1f c byp = 0.01f 900 1000 vo2 (10mv/div) i l 2 = 300ma vo2 = 2.8v 400s/div vo = 3.3v i load = 300ma 3.6v 4.3v 10mv/div c load = 1f c byp = 0.01f 400s/div vo = 2.8v i load = 300ma 3.5v 4.2v 10mv/div c load = 1f c byp = 0.01f 100s/div vo (25mv/div) i load 300ma 100a vin = 2.8v vo = 1.8v 0.1k 1k 10k 100k 1m frequency (khz) 0 10 20 30 40 50 60 70 80 90 100 psrr (db) vin = 3.6v vo = 1.8v i o = 10ma c byp = 0.1f c load = 1f spectral noise density (nv/ hz ) 1000 100 10 1 0.1 10 100 1k 10k 100k 1m frequency (hz) vin = 3.6v vo = 1.8v i load = 10ma c byp = 0.1f c in = 1f c load = 1f isl9000
8 fn9217.3 august 2, 2006 pin description typical application pin # pin name type description 1 vin analog i/o supply voltage/ldo input: connect a 1 f capacitor to gnd. 2 en1 low voltage compatible cmos input ldo-1 enable. 3 en2 low voltage compatible cmos input ldo-2 enable. 4 cbyp analog i/o reference bypass capacitor pin: optionally connect capacitor of value 0.01 f to 1 f between this pin and gnd to tune in the desired noise and psrr performance. 5 cpor analog i/o por2 delay setting capacitor pin: connect a capacitor between this pin and gnd to delay the por2 output release after ldo-2 output reaches 94% of its specified voltage level. (200ms delay per 0.01 f). 6 gnd ground gnd is the connection to system ground. connect to pcb ground plane. 7por1 open drain output (1ma) open-drain por output for ldo-1 (active-low): internally connected to vo1 through 100k resistor. 8por2 open drain output (1ma) open-drain por output for ldo-2 (active-low): internally connected to vo2 through 100k resistor. 9vo2 analog i/o ldo-2 output: connect capacitor of value 1 f to 10 f to gnd (1 f recommended). 10 vo1 analog i/o ldo-1 output: connect capacitor of value 1 f to 10 f to gnd (1 f recommended). c1, c4, c5: 1f x5r ceramic capacitor c2: 0.1f x7r ceramic capacitor isl9000 vin en1 en2 cbyp cpor vo1 vo2 por2 por1 gnd 10 9 8 7 6 1 2 3 4 5 vin (2.3-6.5v) enable 1 enable 2 vout 1 vout 2 reset 1 reset 2 c1 c2 c3 c4 c5 c3: 0.01f x7r ceramic capacitor off on off on (200ms delay, c3 = 0.01f) (2ms delay) vout 2 too low vout 2 ok vout 1 too low vout 1 ok isl9000
9 fn9217.3 august 2, 2006 block diagram functional description the isl9000 contains two high performance ldo?s. high performance is achieved through a circuit that delivers fast transient response to varying lo ad conditions. in a quiescent condition, the isl9000 adjusts its biasing to achieve the lowest standby current consumption. the device also integrates cu rrent limit protection, smart thermal shutdown protection, st aged turn-on and soft-start. smart thermal shutdown pr otects the device against overheating. staged turn-on and soft-start minimize start-up input current surges without causing excessive device turn-on time. power control the isl9000 has two separate enable pins, en1 and en2, to individually control power to each of the ldo outputs. when both en1 and en2 are low, the device is in shutdown mode. during this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.1 a. when one or both of the enable pins are asserted, the device first polls the output of the uvlo detector to ensure that vin voltage is at least about 2.1v. once verified, the device initiates a start-up sequence. during the start-up sequence, trim settings are first read and latched. then, sequentially, the bandgap, re ference voltage and current generation circuitry power-up. once the references are stable, a fast-start circuit quickly charges the external reference bypass capacitor (connected to the cbyp pin) to the proper operating voltage. after the bypass capacitor has been charged, the ldo?s power-up in their specified sequence. soft-start circuitry integrated into each ldo limits the initial ramp-up rate to about 30 s/v to minimize current surge. vo2 ldo error amplifier is1 1v qen1 ldo-1 ldo-2 por comparator vok1 por1 vref trim vin vo1 vo2 por2 por1 gnd en2 en1 control logic por2 delay por1 delay voltage reference generator bandgap and temperature sensor uvlo vok2 vok1 1.00v 0.94v 0.90v is1 is2 qen1 qen2 vo1 vo2 100k 100k cpor cbyp vo1 ~1.0v vok2 por2 isl9000
10 fn9217.3 august 2, 2006 if en1 is brought high, and en2 goes high before the vo1 output stabilizes, the isl9000 delays the vo2 turn-on until the vo1 output reaches its target level. if en2 is brought high, and en1 goes high before vo2 starts its output ramp, then vo1 turns on first and, the isl9000 delays the vo2 turn-on until the vo1 output reaches its target level. if en2 is brought high, and en1 goes high after vo2 starts its output ramp, then the isl9000 immediately starts to ramp up the vo1 output. if both en1 and en2 are brought high at the same time, the vo1 output has priority, and is always powered up first. during operation, whenever the vin voltage drops below about 1.8v, the isl9000 immediately disables both ldo outputs. when vin rises back above 2.1v, the device re-initiates its start-up sequence and ldo operation will resume automatically. reference generation the reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an rc noise filt er. the filter includes the external capacito r connected to the cbyp pin. a 0.01 f capacitor connected cbyp implements a 100hz lowpass filter, and is recommended for most high performance applications. for the lowest noise application, a 0.1 f or greater cbyp capacitor s hould be used. this filters the reference noise below the 10hz to 1khz frequency band, which is crucial in many noise-sensitive applications. the bandgap generates a zero te mperature coefficient (tc) voltage for the reference divider. the reference divider provides the regulation reference, por detection thresholds, and other voltage references r equired for current generation and over-temperature detection. the current generator provides the references required for adaptive biasing as well as references for ldo output current limit and therma l shutdown determination. ldo regulation and programmable output divider the ldo regulator is implemented with a high-gain operational amplifier driving a pmos pass transistor. the design of the isl9000 provides a regulator that has low quiescent current, fast trans ient response, and overall stability across all operating and load current conditions. ldo stability is guaranteed for a 1 f to 10 f output capacitor that has a tolerance better than 20% and esr less than 200m . the design is performance-optimized for a 1 f capacitor. unless limited by th e application, use of an output capacitor value above 4.7 f is not normally needed as ldo performance improvement is minimal. each ldo uses an independently trimmed 1v reference. an internal resistor divider drops the ldo output voltage down to 1v. this is compared to the 1v reference for regulation. the resistor division ratio is programmed in the factory to one of the following output volt ages: 1.5v, 1.8v, 1.85, 2.5v, 2.6v, 2.7v, 2.8v, 2.85v, 2.9, 3.0, and 3.3v. power-on reset generation each ldo has a separate power-on reset signal generation circuit which outputs to the respective por pins. the por signal is generated as follows: a por comparator continuously monitors the output of each ldo. the ldo enters a power-good state when the output voltage is above 94% of the ex pected output voltage for a period exceeding the ldo pgood entry delay time (see below). in the power-good state, the open-drain porx output is in a high-impedance state. an internal 100k pull-up resistor pulls the pin up to the respective ldo output voltage. an external resistor can be added between the porx output and the ldo output for a faster rise time, however, the porx output should not connect through an external resistor to a supply greater than the associated ldo voltage. the power-good state is exited when the ldo output falls below 90% of the expected output voltage for a period longer than the pgood exit delay time. while power-good is false, the isl9000 pulls the respective por pin low. for ldo-1, the pgood entry delay time is fixed at about 2ms while the pgood exit delay is about 25 s. for ldo-2, the pgood entry and exit delays are determined by the value of the external capacito r connected to the cpor pin. for a 0.01 f capacitor, the entry and exit delays are 200ms and 25 s respectively. larger or sm aller capacitor values will yield proportionately longer or shorter delay times. the por exit delay should never be allowed to be less than 10 s to ensure sufficient immunity against transient induced false por triggering. overheat detection the bandgap provides a proporti onal-to-temperature current that is indicative of the temp erature of the silicon. this current is compared with references to determine if the device is in danger of damage due to overheating. when the die temperature reaches about 145c, one or both of the ldo?s momentarily shut down until the die cools sufficiently. in the overheat condition, only the ldo sourcing more than 50ma will be shut off. this do es not affect the operation of the other ldo. if both ldos source more than 50ma and an overheat condition occurs, both ldo outputs are disabled. once the die temperature fall s back below about 110c, the disabled ldo(s) are re-enabled and soft-start automatically takes place. the isl9000 provides short-circ uit protection by limiting the output current to about 475ma. if short circuited, an output current of 475ma will cause die heating. if the short circuit lasts long enough, the overheat detection circuit will turn off the output. isl9000
11 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9217.3 august 2, 2006 isl9000 dual flat no-lead plastic package (dfn) // nx (b) section "c-c" for odd terminal/side e cc 5 c l terminal tip (a1) bottom view a 6 area index c c 0.10 0.08 side view 0.10 2x e a b c 0.10 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a c n-1 12 plane seating c a a3 nx b d2/2 nx k 9 l m l10.3x3c 10 lead dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.85 0.90 0.95 - a1 - - 0.05 - a3 0.20 ref - b 0.20 0.25 0.30 5, 8 d 3.00 bsc - d2 2.33 2.38 2.43 7, 8 e 3.00 bsc - e2 1.59 1.64 1.69 7, 8 e 0.50 bsc - k0.20 - - - l 0.35 0.40 0.45 8 n102 nd 5 3 rev. 1 4/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. compliant to jedec mo-229-weed-3 except for dimensions e2 & d2.
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